digital multi-phase buck controller asp1212 december 16, 2012 | final | v1.06 1 features ? intel vr11.x compliant digital pwm controller ? programmable 1-phase to 8-phase operation ? customized digital over-clocking features an easy- to -use smbus gamer command and a gamer vid control up to 2.3v, gamer vmax, vid override or track, digital load-line adjust, gamer oc/ovp, gamer off pin and gamer otp ? ir efficiency shaping features a variable gate drive and dynamic phase control ? 1-phase to 4-phase psi for light loads ? adaptive transient algorithm minimizes capacitors ? designed for use with coupled inductors ? enables thermal phase balancing ? smbus fault indicators: ovp, uvp, ocp, otp ? smbus interface for configuring and monitoring; smbus commands include monitoring input current and power ? compatible with ir atl drivers and tri-state drivers ? 9 bytes of nvm storage available for customer use ? +3.3v supply voltage; 0oc to 85oc ambient operation ? rohs compliant, msl level 2 package applications ? intel? vr11.x cpu vrd and vrm; ddr memory ? high performance desktops and servers ? over-clocking and high-efficiency application basic application pwm1 12v vout isen1 irtn1 3.3v psi# psi# salert# scl scl salert# en asp1212 vr_rdy_l1 vr_rdy vid7 to vid0 vr_hot vid7 enable powir stage 1 pwm2 isen2 irtn2 powir stage 2 pwm3 isen3 irtn3 powir stage 3 ... vr_hot vcc pwm8 isen8 irtn8 powir stage 8 figure 1: asp1212 basic application circuit description the asp1212 is an 8-phase digital synchronous buck controller for core regulation of high-performance intel ? vr11.1 and vr11.0 platforms. the asp1212 is fully compliant with vr11.1 including power status indicator (psi) and for improved light load efficiency and accurate current output (imon). the ir asp1212 includes a customized set of digital over- clocking features which require no external components. gaming applications can use the smbus interface to place the vr d ito gae mode to extend vid up to 2.3v with 6.25 mv resolution . the asp1212 deploys a number of efficiency shaping features such as variable mosfet gate drive versus load, programmable psi modes for optimum light-load along with programmable phase shedding to autonomously add/drop phases versus load. asp12 12 supports three ntc temperature sensors to report temperature and trigger vr hot and otp faults. digital thermal balancing allows proportional current imbalance between phases. the asp1212 provides extensive ovp, uvp, ocp and otp fault protection. device and fault configuration parameters are easily defined using the ir power designer gui and stored in on-chip non-volatile memory (nvm). the 3-pin smbus interface can be used to monitor a variety of operating parameters on up to seven asp1212 based vrs. the controller includes a unique sensorless and lossless input current monitoring capability. pin diagram sda pwm5 isen6 en vrtn isen8 rcsm psi# isen5 isen4 isen3 pwm6 pwm7 pwm8 vid0 vid1 vid2 vid3 vid4 vid5 vid6 vid7 vcpu vcc scl pwm4 imon vr_ready irtn3 irtn4 irtn6 irtn5 rcsp tsen1 vr_hot pwm3 vinsen isen7 irtn7 irtn8 salert# v18a rres nc vcc 12 3 4 5 6 7 8 9 10 11 12 13 14 48 47 46 45 24 25 26 27 28 17 18 19 20 21 22 23 50 56 55 54 53 52 51 49 40 39 3837 36 35 41 42 isen2 isen1 irtn1 irtn2 pwm2 pwm1 var_gate tsen2 tsen3 15 16 44 43 vcc 3332 31 30 29 34 asp1212 gnd 56 pin 8mmx8mm qfn top view saddr/ gamer_off figure 2: asp1212 package top view downloaded from: http:///
digital multi-phase buck controller asp1212 december 16, 2012 | final | v1.06 2 ordering information asp1212- ? ? ? ? ? package tape & reel qty part number qfn 3000 asp1212-n80nt 1 qfn 3000 asp1212-n60nt 1 qfn 3000 asp1212-n40nt 1 qfn 3000 ASP1212-N20NT 1 notes: 1. idiates ustomer specific configuration file. sda pwm5 isen6 en vrtn isen8 rcsm psi# isen5 isen4 isen3 pwm6 pwm7 pwm8 vid0 vid1 vid2 vid3 vid4 vid5 vid6 vid7 vcpu vcc scl pwm4 imon vr_ready irtn3 irtn4 irtn6 irtn5 rcsp tsen1 vr_hot pwm3 vinsen isen7 irtn7 irtn8 salert# v18a rres nc vcc 12 3 4 5 6 7 8 9 10 11 12 13 14 48 47 46 45 24 25 26 27 28 17 18 19 20 21 22 23 50 56 55 54 53 52 51 49 40 39 38 37 36 35 41 42 isen2 isen1 irtn1 irtn2 pwm2 pwm1 var_gate tsen2 tsen3 15 16 44 43 vcc 33 32 31 30 29 34 asp1212 gnd 56 pin 8mmx8mm qfn top view saddr/ gamer_off figure 3: asp1212 top view enlarged t C tape & reel x C mode id xx C configuration file id a C amd ; n C nvidia downloaded from: http:///
digital multi-phase buck controller asp1212 december 16, 2012 | final | v1.06 4 typical applications block diagrams +3.3v v_cpu 3 30 40 45 7 8 18 13 27 asp1212 14 19 20 21 22 23 24 25 26 9 32 33 36 47 34 35 vinsen pwm4 pwm5 pwm3 pwm 2 pwm1 isen5 vid5 vid6 vid1 vid3 vid4 vid2 vid0 vid7 imon vr_ready vcpu psi# vcc rres en v18a vrtn from cpu irtn3 isen4 2 1 55 irtn1 rcsp irtn2 rcsm isen3 isen2 isen1 irtn4 +12v vvvvv vv v v from system l o a d v vrtn r_imon c_imon rcs ccs r series r series r th r vin_1 r vin_2 53 54 51 52 49 50 irtn5 pwm6 isen6 irtn6 48 37 45 46 28 vr_hot tsen1 r th 6 saddr/ gamer_off 15 salert# +3.3v 16 17 scl sda smbus v v 10 gnd 31 nc 56 v 29 var_gate to cpu to cpu pwm7 isen7 irtn7 38 43 44 pwm8 isen8 irtn8 39 41 42 tsen2 r th 11 tsen3 r th 12 12v v v_vgd optional variable gate drive circuit hvcc lo_gate hi_gate vcc gnd pwm lvcc boot switch mode chl8510 12v v v v_vgd hvcc lo_gate hi_gate vcc gnd pwm lvcc boot switch mode chl8510 12v v v v_vgd hvcc lo_gate hi_gate vcc gnd pwm lvcc boot switch mode chl8510 12v v v v_vgd hvcc lo_gate hi_gate vcc gnd pwm lvcc boot switch mode chl8510 12v v v v_vgd hvcc lo_gate hi_gate vcc gnd pwm lvcc boot switch mode chl8510 12v v v v_vgd hvcc lo_gate hi_gate vcc gnd pwm lvcc boot switch mode chl8510 12v v v v_vgd hvcc lo_gate hi_gate vcc gnd pwm lvcc boot switch mode chl8510 12v v v v_vgd hvcc lo_gate hi_gate vcc gnd pwm lvcc boot switch mode chl8510 12v v v v_vgd hvcc lo_gate hi_gate vcc gnd pwm lvcc boot switch mode chl8510 figure 5 : 6-phase vrd using asp1212 controller and chl8510 mosfet dr ivers downloaded from: http:///
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